1. Field of the Invention
The present invention is related to microprocessor-based computers, and, more particularly, to computers having a shared address, data and control bus for providing access to a memory storage unit to store instructions and data therein and to retrieve instructions and data therefrom. Specifically, the present invention is related to bus arbitration units that determine which of many devices is granted access to a shared bus, such as an AT-type shared bus as used in an IBM.RTM.PC-AT or a compatible computer system.
2. Description of the Related Art
There are many types of computers ranging in size and performance from relatively inexpensive hand-held calculators to large and powerful "mainframe" computers costing millions of dollars. The present invention relates to a type of computer system that is commonly referred to as a microprocessor-based computer system and is often referred to as a "personal computer", or PC, although such microprocessor-based computer systems are used more and more frequently in business, industry, government and other applications where minicomputers and smaller mainframe computers were previously used. As used herein, a microprocessor-based computer system refers to a computer system that comprises a mass-produced integrated circuit microprocessor, such as, for example, the Intel.RTM. 80.times.86 family (i.e., the 8086, the 80286, the 80386, and other integrated circuits). The integrated circuit microprocessor provides the computational power for such a computer system, but it will be understood by one skilled in the art that the successful operation of such a computer system depends upon a number of supporting circuits that control the data inputs and outputs to and from the microprocessor and that provide the microprocessor with sequences of instructions to perform.
In a typical computer system based upon the 80286 microprocessor, for example, the memory of the computer system is the focal point of the system rather than the microprocessor. The microprocessor retrieves instructions and data from the memory and stores data into the memory. The memory of the computer system typically comprises read-only memory (ROM) that is non-volatile and that provides the microprocessor with instructions when the computer system is first powered up or immediately after the computer system is reset. The memory of the computer system also includes random access read/write memory (RAM) that provides substantially larger amounts of data storage. In addition to the microprocessor, various other devices, such as a floppy disk controller, transfer data directly to and from the memory.
In some larger computer systems, such as many mainframe computers, the memory was a separate unit from the processor and other devices that used the memory. In order to provided access to the memory, each of the users, including the processor, is provided with a port to the memory by which address and data are transferred to and from the memory. The memory unit typically has its own control unit to select the device to be provided access at any one time and to provide any necessary memory management functions, such as memory refresh, as in the case of dynamic RAM. Access to the memory in such a manner is commonly referred to as direct memory access (DMA), and this term is generally used to refer to as providing access to the memory without having to transfer data through the microprocessor. For example, in many input/output devices, such as a disk drive, the data transfer rates are often too fast to be handled by the processor. Furthermore, the overhead of having the processor handle the input and output is undesirable as the processor in such large mainframe systems can continue to process other data, perhaps to and from another bank of memory.
In the considerably smaller microprocessor-based computer systems that are the subject of the present application, the memory of the computer system is not a separate unit. Rather, the memory typically resides in the same enclosure as the microprocessor and other devices and is coupled to the microprocessor and other devices by a shared address, data and control bus. As is well known in the art, the address, data and control bus is the heart of the entire computer system. In order for the microprocessor to operate, it must apply the address of an instruction to the shared bus and receive an instruction or series of instructions from the memory via the same shared bus. Thereafter, during the course of executing an instruction, the microprocessor will typically transfer bytes of data to and from the memory via the same shared bus. Furthermore, as set forth above, other devices, such as a floppy disk controller, or the like, transfer data directly to and from the memory via the same shared bus. Finally, the typically read/write memory in a microprocessor-based computer system is dynamic memory. Such a memory retains the data stored therein for only a short amount of time unless the data is "refreshed" by periodically accessing certain sequential addresses in the integrated circuits that comprise the dynamic memory in so-called refresh cycles. Although data is generally not transferred to and from the memory during these refresh cycles, it is necessary in some systems to apply an address to the shared bus as part of a refresh cycle. The microprocessor-based computer system includes refresh circuitry that controls the timing and selection of addresses to periodically refresh the dynamic memory circuits.
In order to provide access to the memory by each of the users (i.e., the microprocessor, the refresh circuitry, the floppy disk controller, and other users), each of the users includes bus interface circuits that are connected to the bus at the same time, but which are activated at different times so that only a single user can affect the contents of the bus. Frequently, such interface circuits are so-called tri-state circuits that have an active state in which they operate to apply one of two logic levels to the shared bus and have an inactive state in which they present a high impedance to the shared bus and thus have no effect on the operation of the bus.
In order to assure that the interface circuits from only one user are active at any one time, a typical microprocessor-based system includes a bus arbitration circuit that receives bus requests from the users connected to the bus and selects one of the users to control the bus at any one time. When a user is granted control of the shared bus, the user operates in conjunction with the memory timing to apply addresses to the shared bus and to transfer data to or receive data from the memory via the shared bus.
It should be understood that in most microprocessor-based computer systems the microprocessor is the most intensive user of the shared bus. Thus, in the Intel 80.times.86 family of microprocessors, the microprocessor includes control signals that determine whether the microprocessor is exerting control over the shared bus or is relinquishing the shared bus to other users. In particular, the microprocessor and its associated clock and timing circuitry includes a HOLD control signal input which can be activated by a bus arbitration circuit, or the like, to indicate that another user is requesting access to the shared bus, and includes a HLDA (hold acknowledge) control signal output that indicates that the microprocessor has finished its current cycle and is willing to relinquish the shared bus, at least temporarily. When the HLDA control signal is received, the bus arbitration circuit grants control of the shared bus to the requesting user having the highest priority (e.g., the refresh circuit, the floppy disk controller circuit, and so on).
The foregoing bus arbitration scheme is sometimes referred to as "cycle stealing" because the bus arbitration circuit is stealing a memory cycle from the microprocessor and granting the memory cycle to another user on the shared bus. In known shared bus arbitration schemes, such cycle stealing is performed only one or a few cycles at a time. For example, the microprocessor has the control of the bus returned to it after the requesting user has accessed the bus for one or more predetermined memory cycles. This system of limiting the grant of the bus to only one or a few memory cycles has been used in known systems a means of preserving the operational integrity of the microprocessor-based computer system. If a user other than the microprocessor is granted control of the shared bus for an extended amount of time (i.e., a large number of memory cycles), the microprocessor would no longer have any control over the operation of the entire system. By returning control of the shared bus to the microprocessor on a periodic basis, the microprocessor can monitor the activities of the other users. More importantly, the microprocessor can process time critical data, such as clock interrupts, and the like.
Although the cycle-stealing arbitration system described above, has the advantage of being relatively immune from system failure caused by the loss of the shared bus by the microprocessor, such arbitration systems suffer from excessive time overhead. In other words, the time required for the bus arbitration circuitry to recognize a request from a user and send the HOLD control signal to the microprocessor; the time required for the microprocessor to recognize the HOLD control signal, finish its current cycle, relinquish the shared bus, and activate the HLDA control signal; the time required for the bus arbitration circuitry to grant control of the shared bus to the requesting user is lost time which becomes significant when accumulated over a large number of user requests. Furthermore, in systems having more than one user other than the microprocessor and the refresh circuitry, the other users must continually vie for priority to use the shared bus. Thus, in microprocessor-based computer systems, such as an AT-type computer system, where the memory refresh operation uses the shared bus, the so-called burst mode of data transfer, in which large quantities of data are transferred to and from the memory, is effectively unknown. Rather, such data is transferred one or two bytes at a time on a cycle stealing basis. The DMA provided by exemplary microprocessor-based computer systems is notoriously slow. In many microprocessor-based systems, the DMA is sufficiently slow that large amounts of data at high data rates, such as to and from a hard disk drive, are transferred through the microprocessor using programmed input and output rather than using the DMA provided by the known bus arbitration circuitry.
Thus, it can be seen that a need exists for an improved bus arbitration circuit that will provide faster and more efficient access to the shared address, data and control bus while maintaining the operational integrity of the microprocessor-based computer system.